From Sabre White Paper:
"B. Rendering the Data into the DAC clock domain
The I2S and DSD are clocked data streams, they do not
require the method used by the SPDIF interface, but they
result in the same thing: similar to the output of the SPDIF
decoder, at a certain asynchronous time, they present to the
downstream processor the new bit or word from the interface.
Rather than trying to lock a PLL to the data rate of this
interface signal, the Sabre DSP uses the arrival time of the
data as a gating signal for the first part of the processing.
Specifically, we now need to apply a filter to the digital data
we must remove the image that will be created when we upsample
the data to our much higher clock rate. This filter
involves a number of cycles of the DSP. One desirable
consequence of this method is that the over-sampling filter
time constant tracks the data rate. The data we have after this
process is, of course, mathematically correct, but if we use this
data in the higher clock domain we will have a great deal of
noise, since as soon as we try to sample the data we must
decide at which edge of our high speed clock this data is to be
used. That choice is never correct this sample delivered from
the interface is supposed to be at some point between our high
speed clock edges. The problem then is this: we have the data
stripped off the transport medium the data is mathematically
correct but we dont know where in time this data is supposed
to be, and even if we did we cannot snap it to our high speed
clock because that represents a quantization in time and hence
noise. The conventional solution is well known: first a digital
PLL is used to remove the jitter of the incoming data (since it
will suffer from jitter in the transport clock) and then a polyphase
filter is employed to rate-convert the signal8 into the
new clock domain. These kinds of sample rate converters
work well but they are limited to certain ranges of operation
(they have a limited ratio of rate conversion typically about
8:1) and a DNR less than that in the digital data itself. The
Sabre DAC rate converter has two advantages compared to the
poly-phase filter approach and is described in great detail in
the pending patent. Firstly the rate conversion is unlimited
allowing the Sabre to always achieve a conversion into its
7 200nS is even greater than the nominal SPDIF clock period but
nevertheless the SPDIF interface correctly decodes the data stream if its FM
modulation is at a sufficiently low frequency.
8 For an introduction to this technique see the Analog Devices AD1896.
exceptionally high clock rate (as much as 40Mhz) from as
little as 4Khz in one step; and secondly, the process is
essentially perfect to the bit level the output DNR exceeds
175dB and the THD is correspondingly high.
As well as sample rate conversion the Sabre has a
proprietary jitter reduction circuit that operates with the rate
converter and is able to achieve a 100% jitter rejection. These
two steps: jitter rejection and rate conversion; are able to take
the burst mode over-sampled filter output into the precisely
correct clock edge of the high speed clock. Audio data from
all sources is now in the high speed clock domain and sent to
the modulator."
Sabre has an internal clock, so all upsampling is async.
